This invention relates generally to semiconductor integrated circuit fabrication, and more particularly the invention relates to measurement of electromigration of metal atoms in metal interconnect lines in integrated circuits.
Electromigration is the migration or movement of metal atoms within a conductor in response to an electrical current or electron wind within the conductor. The migration of the metal atoms is dependent on several factors but the dominant factors for a given material are current density and temperature. A consequence of this metal migration is the formation of areas from which the metal has migrated and consequently left voids which contain no metal. A related consequence of this metal migration is the formation of areas to which the metal has migrated and built up in an excess quantity which are often referred to as hillocks or extrusions.
Given the proper conditions, electromigration can occur in a metal wire eventually resulting in the formation of a void which grows until it completely spans the diameter of the wire resulting in an open circuit. The time it takes the material under stress to fail is termed the xe2x80x9ctime to failurexe2x80x9d. The equation relating time to failure to both current density and temperature is well known and is commonly referred to as Black""s Equation., as follows:
MTF=AJxe2x88x92n exp(Ea/kT)
where
MTF=mean time to failure
A=proportionality constant
J=current density
n=current exponent
Ea=activation energy
T=temperature
k=boltzmans constant
The xe2x80x9ctime to failurexe2x80x9d is of great interest in the integrated circuit industry because electromigration failures can be the main cause of product failures in the field. The only method available to measure electromigration lifetime until now has been to force a known current through a metal line of a given cross sectional area and at a given temperature until failure. The current density through the metal line is calculated by dividing the current by the cross sectional area of the metal conductor 8 as shown in FIG. 1.
Failure is usually defined as a specific change in the resistance of the metal line. This change in resistance can be very slight or in the extreme it can be an open circuit. The only way to know the current density is to know both the current and the cross sectional area of the metal conductor. The current is forced by the user so this is known. The metal test structure is designed by the user so in theory the width of the test structure is known. And the metal is deposited by the user so again in theory the metal thickness is known.
Normal lifetime goals for metal lines in integrated circuits is on the order of 10 years. Therefore, to obtain failures in a reasonable amount of time in the lab, these failures are accelerated on these specific test structures by using higher than normal current densities and higher than normal temperatures. By selecting several accelerated current densities and several accelerated temperatures the failure rates can be extrapolated back to normal use conditions. This prediction of lifetime in the field is the ultimate goal of this reliability test.
The process which is used today to both generate these test structures and then test them is long and arduous. A serious consequence of the length of time it takes to complete the construction of the test structure and then the length of time it takes to test the test structure is the large time constant which results in the feedback of this information to the process to control the parameters which influence the elecromigration behavior. The prior art requires the use of a very specific test structure which must be created in the thin film long after the thin film has been deposited. It can easily take months to obtain the information to feedback to the process. In this time, several millions of dollars worth of semiconductor wafers will have been processed which are potentially at risk of being out of specification and therefore unreliable in the field. The goal of in line electromigration testing is to shorten this time and reduce the amount of material in process which is at risk.
In accordance with the invention, a test wafer is provided during metal deposition in the batch fabrication of integrated circuit wafers by providing one wafer having an insulating layer with a step pattern etched therein with the step height being greater than twice the thickness of the deposited metal. The cross section allows metal deposition on the top of the step, which is used for electromigration test, but no metal is deposited on the vertical side walls of the step, the vertical side walls having a height of at least twice the metal thickness. The resulting test structure can have a conventional electromigration test performed as soon as, the test wafer emerges from the metal deposition system.
In an alternative embodiment, a test wafer is provided having an insulating layer on which is deposited a metal layer during the metal deposition step in the batch fabrication of integrated circuits. The test wafer is then exposed to a focused laser beam which selectively ablates metal to form a test conductor for electromigration testing. Alternatively, an ultrasonic probe can be used rather than the laser in forming the test conductor by selective erosion of the metal.
In another embodiment of the invention, a test wafer is again provided with an insulating layer on which is deposited a metal layer during the metal deposition step, but the metal layer is not processed further. The metal layer is then contacted by two opposing elongated contacts to which voltages are impressed for the electromigration testing. Metal will remain under the elongated contacts, but near the voltage source contact will be an elongated region where metal has been moved due to electromigration. The elongated contacts can be wires or a plurality of point sources to create a pseudo line source.
The invention and objects and features thereof will be more readily apparent from the detailed description and appended claims when taken with the drawings.